The present invention relates generally to switched capacitor circuits, including SAR ADCs (successive approximation register analog to digital converters), and more particularly to an improved technique for avoiding charge leakage through integrated circuit substrate diodes caused by analog summing node voltages swinging outside of an acceptable range in a switched capacitor circuit, an SAR ADC, and still more particularly to SAR ADCs that are simpler and less expensive than those available in the prior art.
Prior Art FIG. 1A is a simplified diagram of a basic well-known single-ended SAR ADC which executes a conventional SAR algorithm to convert an analog input voltage VIN to a digital output signal DOUT. For example, see FIGS. 13.5, 13.6, and 13.7 and associated text in “Analog Integrated Circuit Design” by David Johns and Ken Martin (1997 John Wiley & Sons, Inc.).
The SAR ADC in Prior Art FIG. 1A includes a sample/hold circuit 19 that receives input voltage VIN. The output of sample/hold circuit 19 is applied to the (+) input of a comparator 20. The output 23 of comparator 20 is applied to an input of SAR/control logic circuitry 21 which controls operation of a basic SAR algorithm to sequentially generate N bits b1, b2 . . . bN. The N bits b1, b2 . . . bN control DAC 16 so as to cause its output voltage VDAC to be precisely equal to VIN. At the end of the analog to digital conversion process, SAR/control logic 21 generates an “End of Conversion” signal EOC, and the N bits b1, b2 . . . bN may be taken as the digital output signal DOUT into which VIN has been converted.
The output of sample/hold circuit 19 is compared with VDAC by comparator 20. The output of comparator 20 causes SAR/control logic 21 to determine, in accordance with a SAR algorithm, the values of bits b1, b2, . . . bN in such a way as to cause DAC 16 to force the value of VDAC on conductor 13 to become closer and closer to the value of VIN as the SAR conversion cycle progresses. The basic SAR conversion process begins after completion of the sample and hold operation. First, bit b1 is set to “1”, and the other bits b2, b3 . . . bN are set to “0”s. DAC 16 generates a mid-level “half-voltage” equal to a value VREF/2 with which the sampled input signal VIN is compared, where VREF represents the full-scale value of VIN. Comparator 20 causes the final value of bit b1 to be set to a “1” if VIN is greater than VDAC but otherwise b1 is set to a “0”, and in either case the remaining bits b2, b3 . . . bN are set to “0”s. In the next conversion cycle, the SAR algorithm causes comparator 20 to test bit b2 in the same manner. DAC 16 generates an adjusted value of VDAC to which the sampled input signal VIN is compared. Comparator 20 causes the final value of bit b2 to be set to a “1” if VIN is greater than VDAC but otherwise b2 is set to a “0”, and in either case the remaining bits b3, b4 . . . bN are set to “0”s. Essentially the same procedure is repeated during each of the remaining bits cycles for each of the remaining bits b3, b4 . . . bN, respectively.
The closest prior art is believed to include U.S. Pat. No. 6,667,707 entitled “Analog-to-Digital Converter with the Ability to Asynchronously Sample Signals without Bias or Reference Voltage Power Consumption” issued Dec. 23, 2003 to Mueck et al., and incorporated herein by reference. Prior Art FIG. 1B herein is essentially the same as FIG. 4 of the Mueck et al. patent, and shows an improved differential CDAC implementation of the SAR ADC of Prior Art FIG. 1A.
In Prior Art FIG. 1B, a differential input charge redistribution SAR ADC system 300 samples a pair of input voltages, Vinp and Vinn, with respect to a common mode bias voltage, Vcm. Under the control of a SAR algorithm/engine, a sequence of binary decisions is produced at the output OUT which correspond to the digital equivalent of Vrefp-Vrefn. ADC system 300 includes two DACs, DAC-P and DAC-N, a comparator 32, and an SAR engine (not shown) to drive the DACs. Note that the CDAC arrays perform the sample/hold function of sample/hold circuit 19 in Prior Art FIG. 1A, in addition to being used for the bit decision “feedback” function of providing CDAC output voltages at the comparator inputs in response to the input voltages. In this example, each DAC comprises a 6-bit binary-weighted capacitor array 34P, 34N, where the total capacitance of each array 34P, 34N is C. The DACs further include two corresponding sets 36P, 36N of switches to connect the respective DAC inputs to Vinp/n, and corresponding sets 38P, 38N of switches to connect the respective DAC inputs to Vrefp/n, and further include switches 20P, 20N to connect the DAC outputs, TOP-P, TOP-N, to Vcm. Each of the weighted capacitor arrays 34N associated with DAC-N and 34P associated with DAC-P includes capacitors C1, C2, C3, C4, C5, C6 and C7 having capacitances of C1=C/2, C2=C/4, C3=C/8, C4=C/16, C5=C/32, C6=C/64 and C7=C/64, the sum of which is approximately equal to C. Each of switch sets 36N associated with DAC-N and 36P associated with DAC-P includes switches S1, S2, S3, S4, S5 and S6. Each of switch groups 38N associated with DAC-N and 38P associated with DAC-P includes switches S21, S22, S23, S24, S25 and S26. The DAC outputs TOP-P, TOP-N, provide input voltages to comparator 32. The plates of the capacitors directly connected to TOP-P, TOP-N are referred to as “top plates”, and the other capacitor plates are referred to as the “bottom plates.” The switches to Vcm are referred to as the “top-plate switches” 20P and 20N.
During operation, an input voltage is sampled as charge across the input capacitors. With the DAC bottom plates connected to the input voltage Vinp and Vinn through switches and 36P 36N when the top-plate switches 20P and 20N are closed, the DAC is said to be “sampling the input”, and the instant at which the top plate switches open, the DAC is said to have “taken the sample”. After sampling the input voltage, the SAR ADC 300 carries out an iterative SAR process. Using the P-side of the circuit as an example, the SAR iterative process begins by connecting the bottom plate of each of the capacitor array 34P capacitors C1 . . . C6, through its corresponding switch S1 . . . S6 in switch bank 36P and a corresponding switch S21 . . . S26 in switch bank 38P, to either the positive reference voltage Vrefp or the negative reference voltage Vrefn. Each capacitor, e.g. C4, represents one of the bits in the digital output word of the ADC 300, the most significant bit (MSB) of which corresponds to capacitor C1 and the least significant bit (LSB) of which corresponds to capacitor C6.
In Prior Art FIG. 1B, a bit has a binary value of 1 when the bottom plate of the associated capacitor, e.g. C4, is connected to the positive reference voltage Vrefp and the bit has a binary value of 0 when the bottom plate of the capacitor, e.g. C4, is connected to the negative reference voltage Vrefn through switch bank 38. In this example, switch S4 would get switched to connect capacitor C4 to the Vref set and switch S24 would get aligned to connect capacitor C4 to either Vrefp or Vrefn, depending on whether C4 was to represent a logical 1 or 0, respectively. Through such a series of SAR iterations, starting with the MSB capacitor and ending with the LSB capacitor, during each iteration each capacitor is switched to either Vrefp or Vrefn such that the top plate voltages TOP-P and TOP-N converge with each iteration. When the iterations have completed, the last-used digital word (the value of the bits to which the capacitors were connected) is selected as the output of the ADC 300.
The DAC top plates are sampled to Vcm, which is an arbitrary but constant voltage and which can be VSS for zero-power sampling. During sampling, TOP-P and TOP-N will be nominally held at approximately Vcm by the top plate switches.
In Prior Art FIG. 1B, after sampling the input voltage but prior to beginning the SAR process, the comparator output directs the SAR algorithm to modify the DAC inputs such that the two DAC outputs converge. The common mode output voltage of the DACs is boosted during only some of the iterations. The inputs to the comparator are capacitively boosted by coupling the common mode voltage boost to the comparator inputs during some of the iterations to thereby avoid associated leakage of sampled charge through the substrate diodes. However, as the SAR process progresses, the voltage differences between TOP-P and TOP-N become less and less, to a point where the voltage on an output node of a DAC no longer can turn on a substrate diode, and then the capacitive boost to the comparator inputs is removed.
For conventional Zero-Power Sampling SAR ADCs such as the one shown in Prior Art FIG. 1B, the summing node voltages at CDAC top plate can swing far beyond either the supply or the ground voltage. In SAR ADC 300 of Prior Art FIG. 1B, this causes leakage of the re-distributed charge from the CDAC capacitors to discharge through substrate diodes associated with the top-plate switches, thereby causing conversion errors. In Prior Art FIG. 1B, two switches are connected to Vcm at the inputs of comparator 32. Boosting capacitors 311P and 311N and associated additional circuitry, including switches 313P and 313N, are required to keep the summing node voltages at the inputs of comparator 32 within an acceptable range by boosting/shifting the summing node voltages from unacceptable out-of-range values to acceptable values, i.e., values which are no more than approximately 100 mV below VSS, to prevent junction leakage into the substrate. Also, the conventional SAR algorithm is modified in order to accommodate the boosting/shifting operation by operatively connecting the boost capacitors for a number of initial bit cycles and then operatively disconnecting the boost capacitors. The summing node voltages must be monitored and controlled to keep the common mode voltages of the summing nodes within an acceptable range.
Thus, there is an unmet need for a switched-capacitor circuit and method which provide a fixed common mode voltage component on a summing conductor, the voltage of which otherwise would exceed a safe operating voltage range during normal operation.
There also is an unmet need for a SAR ADC and method which do not require boosting of analog summing voltages at the input of the comparator to prevent leakage from the analog summing nodes through substrate diodes of an integrated circuit due to out-of-range values of the analog summing voltages.
There also is an unmet need for a SAR ADC and method which do not require boosting of analog summing voltages at the input of the comparator to prevent leakage from the analog summing nodes through substrate diodes of an integrated circuit due to out-of-range values of the analog summing voltages and which are simpler and less costly than the closest prior art SAR ADCs.
There also is an unmet need for a SAR ADC and method which do not require boosting of analog summing voltages at the input of the comparator to prevent leakage from the analog summing nodes through substrate diodes of an integrated circuit due to out-of-range values of the analog summing voltages and which do not require modification of the normal SAR ADC decision process.
There also is an unmet need for a SAR ADC and method which avoids the reduced SNR (signal to noise ratio) associated with the use of capacitor boosting of analog summing voltages at the input of a comparator in the prior art in order to prevent leakage from the analog summing nodes substrate diodes.
There also is an unmet need to avoid the need to provide special circuitry for monitoring and controlling a common mode voltage of a summing conductor of a circuit such as an ADC, a switched capacitor filter, a switched capacitor integrator, or a switched capacitor amplifier.